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CY2V995
2.5/3.3V 200-MHz Multi-Output Zero Delay Buffer
Features
* * * * * * * * * * * * * * 2.5V or 3.3V operation Split output bank power supplies Output frequency range: 6 MHz to 200 MHz Output-output skew: < 150 ps Cycle-cycle jitter: < 100 ps Selectable positive or negative edge synchronization 8 LVTTL outputs driving 50 terminated lines LVCMOS/LVTTL over-voltage tolerant reference input Selectable phase-locked loop (PLL) frequency range and lock indicator (1-6,8,10,12)x multiply and (1/2,1/4)x divide ratios Spread-Spectrum-compatible Power-down mode Industrial temperature range: -40C to +85C 44-pin TQFP package
Description
The CY2V995 is a low-voltage, low-power, eight output, 200-MHz clock driver. It features function necessary to optimize the timing of high-performance computer and communication systems. The user can program the frequency of the output banks through nF[0:1] and DS[0:1] pins. Any one of the outputs can be connected to feedback input to achieve different reference frequency multiplication and divide ratios and zero input-output delay. The device also features split output bank power supplies which enable the user to run two banks (1Qn and 2Qn) at a power supply level different from that of the other two banks (3Qn and 4Qn). Additionally, the PE pin controls the synchronization of the output signals to either the rising or the falling edge of the reference clock.
Block Diagram
TEST PD# PE FS VDDQ1
Pin Configuration
PLL
FB DS1:0
LOCK
/N
3 3
4F1
1Q0
1F1:0 1Q1
sOE# PD# PE VDDQ4 VDDQ4 4Q1 4Q0 VSS VSS VSS
2Q0 2F1:0 2Q1
3F1:0
3 3 /K
3Q0 3Q1 VDDQ3
44 43 42 41 40 39 38 37 36 35 34 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 2122
4F0
3F1 3F0
REF
FS VDD REF VSS TEST 2F1 2F0 1F1 33 32 31 30 29 28 27 26 25 24 23 1F0 DS1 DS0 LOCK VDDQ1 VDDQ1 1Q0 1Q1 VSS VSS VSS
3
3
CY2V995
4F1:0
3 3 /M
4Q0 4Q1
VDDQ4 sOE#
Cypress Semiconductor Corporation Document #: 38-07435 Rev. *A
*
3901 North First Street
*
San Jose, CA 95134 * 408-943-2600 Revised January 19, 2004
VSS 3Q1 3Q0 VDDQ3 VDDQ3 FB VDD VDDQ1 2Q1 2Q0 VSS
CY2V995
Pin Description
Pin 39 17 37 2 Name REF FB TEST sOE# I I I I, PD I/O[1] Type LVTTL/ LVCMOS LVTTL 3-Level LVTTL Reference Clock Input. Feedback Input. When MID or HIGH, disables PLL (except for conditions of note 3). REF goes to all outputs. Set LOW for normal operation. Synchronous Output Enable. When HIGH, it stops clock outputs (except 2Q0 and 2Q1) in a LOW state (for PE = H or M) - 2Q0 and 2Q1 may be used as the feedback signal to maintain phase lock. When TEST is held at MID level and sOE# is high, the nF[1:0] pins act as output disable controls for individual banks when nF[1:0] = LL. Set sOE# LOW for normal operation. Selects Positive or Negative Edge Control and High or Low output drive strength. When LOW / HIGH the outputs are synchronized with the negative/positive edge of the reference clock, respectively. Please see Table 8. Select frequency of the outputs. Please see Tables 3, 4, 5, and 7. Selects VCO operating frequency range. Please see Table 6. Four banks of two outputs. Please see Table 5 for frequency settings. Select feedback divider. Please see Table 1. Power-down and reference divider control. When LOW, shuts off entire chip. Please see Table 2 for settings. PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the input. Power supply for Bank 4 output buffers. Please see Table 8 for supply level constraints Power supply for Bank 3 output buffers. Please see Table 8 for supply level constraints Power supply for Bank 1 and Bank 2 output buffers. Please see Table 8 for supply level constraints Power supply for the internal circuitry. Please see Table 8 for supply level constraints Ground Table 1. Feedback Divider Settings DS[1:0] LL LM LH ML MM MH HL HM HH N-Feedback Input Divider 2 3 4 5 1 6 8 10 12 Permitted Output Divider Connected to FB[4] 1 or 2 1 1,2 or 4 1 or 2 1,2 or 4 1 or 2 1 or 2 1 1 Description
4
PE
I, PU
LVTTL
34, 33, 36, 35, nF[1:0] 43, 42, 1, 44 41 26,27,20,21, 13,14,7,8 32, 31 3 30 5,6 15,16 19,28 18,40 FS nQ[1:0] DS[1:0] PD# LOCK
I I O I I, PU O
3-Level 3-Level LVTTL 3-Level LVTTL LVTTL Power Power Power Power Power
VDDQ4[2] PWR VDDQ3 [2] PWR VDDQ1[2] PWR VDD[2] PWR PWR
9-12, 22-25, 38 VSS
Device Configuration
The outputs of the CY2V995 can be configured to run at frequencies ranging from 6 MHz to 200 MHz. The feedback input divider is controlled by the 3-level DS[0:1] pins as indicated in Table 1.
Notes: 1. `PD' indicates an internal pull-down and `PU' indicates an internal pull-up. 2. A bypass capacitor (0.1F) should be placed as close as possible to each positive power pin (<0.2"). If these bypass capacitors are not close to the pins their high frequency filtering characteristic will be cancelled by the lead inductance of the traces. 3. When TEST = MID and sOE# = HIGH, PLL remains active with nF[1:0] = LL functioning as an output disable control for individual output banks. Skew selections remain in effect unless nF[1:0] = LL. 4. Permissible output division ratios connected to FB. The frequency of the REF input will be FNOM/N when the part is configured for frequency multiplication by using an undivided output for FB and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
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CY2V995
Table 2. Power-down Mode PD# H L CY2V995 Enabled Power Down Table 6. Frequency Range Select FS L M H PLL Frequency Range 24 to 50 MHz 48 to 100 MHz 96 to 200 MHz
In addition to the feedback dividers, the CY2V995 includes output dividers on Bank3 and Bank4, which are controlled by 3F[1:0] and 4F[1:0] as indicated in Table 3 and 4, respectively. Table 3. Output Divider Settings - Bank 3 3F[1:0] LL[5] HH Other K - Bank3 Output Divider 2 4 1
The PE pin determines Whether the outputs synchronize to the rising or the falling edge of the reference signal, as indicated in Table 7. Table 7. PE Settings PE L H Synchronization Negative Positive
Table 4. Output Divider Settings - Bank 4 4F[1:0] LL[5] HH Other M - Bank4 Output Divider 2 Inverted[6] 1
The CY2V995 features split power supply buses for Banks 1 and 2, Bank 3 and Bank 4, which enables the user to obtain both 3.3V and 2.5V output signals from one device. The core power supply (VDD) must be set a level which is equal or higher than that on any one of the output power supplies. Table 8. Power Supply Constraints VDD 3.3V 2.5V VDDQ1[8] 3.3V or 2.5V 2.5V VDDQ3[8] 3.3V or 2.5V 2.5V VDDQ4[8] 3.3V or 2.5V 2.5V
The divider settings, output frequencies, and possible configurations of connecting FB to ANY output are summarized in Table 5. Table 5. Output Frequency Settings Configuration FB Input Connected to 1Qn or 2Qn 3Qn 4Qn Output Frequency 1Q[0:1] and 2Q[0:1][7] N x FREF 3Q[0:1] 4Q[0:1]
Governing Agencies
The following agencies provide specifications that apply to the CY2V995. The agency name and relevant specification is listed below. Agency Name JEDEC IEEE UL-194_V0 MIL Specification JESD 51 (Theta JA) JESD 65 (Skew, Jitter) 1596.3 (Jiter Specs) 94 (Moisture Grading) 883E Method 1012.1 (Therma Theta JC)
N /x (1 / K) x N x (1 / M) x FREF FREF N x (K / M) x FREF
N x K x FREF N x FREF
N x M x FREF N x (M / K) x N x FREF FREF
The 3-level FS control pin setting determines the nominal operating frequency range of the divide-by-one outputs of the device. The CY2V995 PLL operating frequency range that corresponds to each FS level is given in Table 6.
Notes: 5. LL disables outputs if TEST = MID and sOE# = HIGH. 6. When 4Q[0:1] are set to run inverted (HH mode), sOE# disables these outputs HIGH when PE = HIGH or MID, sOE# disables them LOW when PE = LOW. 7. These outputs are undivided copies of the VCO clock. Therefore, the formulas in this column can be used to calculate the VCO operating frequency (FNOM) at a given reference frequency (FREF) and divider and feedback configuration. The user must select a configuration and a reference frequency that will generate a VCO frequency that is within the range specified by FS pin. Please see Table 6. 8. VDDQ1/3/4 must not be set at a level higher than that of VDD. They can be set at different levels from each other, e.g. VDD = 3.3V, VDDQ1 = 3.3V, VDDQ3 = 2.5V and VDDQ4 = 2.5V.
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CY2V995
Absolute Maximum Conditions
Parameter VDD VDD VIN(MIN) VIN(MAX) VREF(MAX) VREF(MAX) TS TA TJ ESDHBM OJC OJA UL-94 MSL FIT Description Operating Voltage Operating Voltage Input Voltage Input Voltage Reference Input Voltage Reference Input Voltage Temperature, Storage Temperature, Operating Ambient Temperature, Junction ESD Protection (Human Body Model) Dissipation, Junction to Case Dissipation, Junction to Ambient Flammability Rating Moisture Sensitivity Level Failure in Time Manufacturing Testing Condition Functional @ 2.5V 5% Functional @ 3.3V 10% Relative to VSS Relative to VDD VDD = 3.3V VDD = 2.5V Non Functional Functional Functional MIL-STD-883, Method 3015 Mil-Spec 883E Method 1012.1 JEDEC (JESD 51) @1/8 in. -65 -40 - 2000 42 74 V-0 1 10 ppm Min. 2.25 2.97 VSS - 0.3 - Max. 2.75 3.63 - VDD + 0.3 5.5 4.6 +150 +85 155 - Unit V V V V V V C C C V C/W C/W
DC Specifications @ 2.5V
Parameter VDD VIL VIH VIHH[9] VIMM[9] VILL[9] IIL I3 Description 2.5 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Input DC Current VIN = VDD/GND,VDD = Max (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU IPD VOL VOH IDDQ IDDPD IDD CIN Input Pull-up Current Input Pull-down Current Output LOW Voltage Output HIGH Voltage VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#) IOL = 12mA, (nQ[0:1]) IOL = 2mA (LOCK) IOH = -12mA,(nQ[0:1]) IOH = -2mA (LOCK) Quiescent Supply Current Power-down Current Dynamic Supply Current Input Pin Capacitance VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH VDD = Max @100 MHz 2.0 2.0 - 10(typ.) 150 4 2 25 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0]) 2.5V 5% REF, FB, PE, PD#, and sOE# Inputs Conditions Min. 2.375 - 1.7 Max. 2.625 0.7 - Unit V V V V V V A A A A A A V V V mA A mA pF
3-Level Inputs VDD- - (TEST, FS, nF[1:0], DS[1:0]) -0.4 (These pins are normally wired to VDD,GND or uncon- V /2 - V /2 + DD DD nected) 0.2 0.2 - -5 - -50 -200 -25 - - 0.4 5 200 50 - - 100 0.4 0.4 -
Note: 9. These Inputs are normally wired to VDD, GND or unconnected. Internal termination resistors bias unconnected inputs to VDD/2.
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CY2V995
DC Specifications @ 3.3V
Parameter VDD VIL VIH VIHH[9] VIMM[9] VILL[9] IIL I3 Description 3.3 Operating Voltage Input LOW Voltage Input HIGH Voltage Input HIGH Voltage Input MID Voltage Input LOW Voltage Input Leakage Current 3-Level Input DC Current 3-Level Inputs (TEST, FS, nF[1:0], DS[1:0]) (These pins are normally wired to VDD,GND or unconected VIN = VDD/GND,VDD = Max (REF and FB inputs) HIGH, VIN = VDD MID, VIN = VDD/2 LOW, VIN = VSS IPU IPD VOL VOH IDDQ IDDPD IDD CIN Input Pull-Up Current Input Pull-Down Current Output LOW Voltage Output HIGH Voltage VIN = VSS, VDD = Max VIN = VDD, VDD = Max, (sOE#) IOL = 12mA, (nQ[0:1]) IOL = 2mA (LOCK) IOH = -12mA,(nQ[0:1]) IOH = -2mA (LOCK) Quiescent Supply Current VDD = Max, TEST = MID, REF = LOW, sOE# = LOW, Outputs not loaded PD#, sOE# = LOW Test,nF[1:0],DS[1:0] = HIGH VDD = Max @100 MHz 2.4 2.4 - 2 mA 3-Level Inputs (TEST, FS,nF[1:0], DS[1:0]) 3.3V 10% REF, PE, PD#, FB and sOE# Inputs Condition Min. 2.97 - 2.0 VDD--0.6 VDD/2-0.3 - -5 - -50 -200 -25 - - Max. 3.63 0.8 - - VDD/2+0.3 0.6 5 200 50 - - 100 0.4 0.4 - V Unit V V V V V V A A A A A A V
Power-down Current Dynamic Supply Current Input Pin Capacitance
10(typ.) 230 4
25
A mA pF
AC Input Specifications
Parameter TR,TF TPWC TDCIN FREF Description Input Rise/Fall Time Input Clock Pulse Input Duty Cycle Reference Input Frequency FS = LOW FS = MID FS = HIGH 0.8V - 2.0V HIGH or LOW Condition Min. - 2 10 2 4 8 Max. 10 - 90 50 100 200 Unit ns/V ns % MHz
Switching Characteristics
Parameter FOR VCOLR VCOLBW tSKEWPR Description Output frequency range VCO Lock Range VCO Loop Bandwidth Matched-Pair Skew[10] Skew between the earliest and the latest output transitions within the same bank. Condition Min. 6 200 0.25 - Max. 200 400 3.5 150 Unit MHz MHz MHz ps
Note: 10. Test Load = 20 pF, terminated to VCC/2. All outputs are equally loaded.
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CY2V995
Switching Characteristics (continued)
Parameter tSKEW0 tSKEW1 tSKEW2 tSKEW3 tSKEW4 tSKEW5 tPART Part-Part Skew Description Output-Output Skew[10] Condition Skew between the earliest and the latest output transitions among all outputs. Skew between the earliest and the latest output transitions among all same class outputs. Skew between the nominal output rising edge to the inverted output falling edge Skew between non-inverted outputs running at different frequencies Skew between nominal to inverted outputs running at different frequencies Skew between nominal outputs at different power supply levels Skew between the outputs of any two devices under identical settings and conditions (VDDQ,VDD,temp,air flow, frequency, etc) Measured at VDD/2 Measured at 2.0V for VDD = 3.3V and at 1.7V for VDD = 2.5V. Measured at 0.8V for VDD = 3.3V and at 0.7V for VDD = 2.5V. Measured at 0.8V-2.0V for VDD = 3.3V and 0.7V-1.7V for VDD = 2.5V Divide by 1 output frequency, FS = L, FB = divide by any Divide by 1 output frequency, FS = M/H, FB = divide by any Min. - - Max. 200 200 Unit ps ps
- - - - -
500 500 500 650 750
ps ps ps ps ps
tPD0 tODCV tPWH tPWL tR/tF tLOCK tCCJ
Ref to FB Propagation Delay[11] Output Duty Cycle Output High Time Deviation from 50% Output Low Time Deviation from 50% Output Rise/Fall Time PLL lock time[12, 13] Cycle-Cycle Jitter
-250 45 - - 0.15 - - -
+250 55 1.5 2.0 1.5 0.5 100 150
ps % ns ns ns ms ps ps
Notes: 11. tPD is measured at 1.5V for VDD = 3.3V and at 1.25V for VDD = 2.5V with REF rise/fall times of 0.5 ns between 0.8V-2.0V. 12. tLOCK is the time that is required before outputs synchronize to REF. This specification is valid with stable power supplies which are within normal operating limits. 13. Lock detector circuit may be unreliable for input frequencies lower than 4MHz, or for input signals which contain significant jitter.
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CY2V995
AC Timing Definitions
tREF tPWH tPWL
REF
tPD
t0DCV
t0DCV
FB
tCCJ1-12
Q
tSKEWPR tSKEW0,1
tSKEWPR tSKEW0,1
OTHER Q
tSKEW1
tSKEW1
INVERTED Q
tSKEW3
tSKEW3
tSKEW3
REF DIVIDED BY 2
tSKEW1,3,4
tSKEW1,3,4
REF DIVIDED BY 4
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CY2V995
AC Test Loads and Waveforms
VDDQ
Output 20pF Output
150
150
20pF
For Lock Output
Figure 1.
For All Other Outputs
tORISE
tOFALL
tORISE
tOFALL
2.0V VTH =1.5V 0.8V tPWL
tPWH
1.7V VTH =1.25V 0.7V
tPWH
tPWL
3.3V LVTTL OUTPUT WAVEFORM
2.5V LVTTL OUTPUT WAVEFORM
Figure 2.
1ns
3.0V 2.0V VTH =1.5V 0.8V 0V
1ns
2.5V 1.7V VTH =1.25V 0.7V 0V
1ns
1ns
3.3V LVTTL INPUT TEST WAVEFORM
Figure 3.
2.5V LVTTL INPUT TEST WAVEFORM
Ordering Information
Part Number CY2V995AC CY2V995ACT CY2V995AI CY2V995AIT 44 TQFP 44 TQFP - Tape and Reel 44 TQFP 44 TQFP - Tape and Reel Package Type Product Flow Commercial, 0 to 70C Commercial, 0 to 70C Industrial,-40 to 85C Industrial,-40 to 85C
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CY2V995
Package Drawing and Dimensions
44-lead Thin Plastic Quad Flat Pack (10 x 10 x 1.0 mm) A44SB
51-85155-*A
All product and company names mentioned in this document are the trademarks of their respective holders.
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(c) Cypress Semiconductor Corporation, 2004. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY2V995
Document History Page
Document Title:CY2V995 2.5/3.3V 200-MHz Multi-output Zero Delay Buffer Document Number: 38-07435 REV. ** *A ECN No. 122627 200501 Issue Date 01/13/03 See ECN Orig. of Change RGL RGL New Data Sheet Changed Pin 5 from VDD to VDDQ4, Pin 16 from VDD to VDDQ3 and Pin 29 from VDD to VDDQ1 Description of Change
Document #: 38-07435 Rev. *A
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